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ds07-12516-4e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89870 series mb89875/p875/pv870 n description the mb89870 series is a line of single-chip microcontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as dual-clock control system, five operating speed control stages, timers, a pwm timer, a serial interface, an a/d converter, an external interrupt, an lcd controller/ driver, and a watch prescaler. n features ?f 2 mc-8l family cpu core ? dual-clock control system ? maximum memory space: 64 kbytes ? minimum execution time: 0.4 m s/10 mhz ? interrupt processing time: 3.6 m s/10 mhz ? i/o ports: max. 45 channels ? 21-bit timebase timer ? 8-bit pwm timer: 1 channel, 1 output channel ? 8/16-bit timer/counter: 2 channels (16 bits 1 channel) ? 8-bit serial i/o: 1 channel ? 10-bit a/d converter: 8 channels ? op amp: 4 channels ? external interrupt (wake-up function): 8 channels (continued) n pac k ag e 80-pin plastic lqfp (fpt-80p-m05) 80-pin plastic qfp (fpt-80p-m06) 80-pin ceramic mqfp (mqp-80c-p01)
2 mb89870 series (continued) ? watch prescaler (15 bits) ? lcd controller/driver: 16 to 24 segments 2 to 4 commons ? power-on reset function ? low-power consumption modes (subclock mode, watch mode, sleep mode, and stop mode) ? lqfp-80 (0.50-mm pitch) and qfp-80 (0.80-mm pitch) package n product lineup (continued) MB89P875 mb89pv870 classification mass production product (mask rom product) one-time prom product piggyback/evaluation product (for development) rom size 16 k 8 bits (internal mask rom) 16 k 8 bits (internal prom) 32 k 8 bits (external rom) ram size 512 8 bits 1 k 8 bits lcd display ram 12 8 bits cpu functions number of instructions: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, 16 bits minimum execution time: 0.4 m s/10 mhz to 6.4 m s/10 mhz, 61.0 m s/32.768 khz interrupt processing time: 3.6 m s/10 mhz to 57.6 m s/10 mhz, 549.3 m s/32.768 khz ports general-purpose i/o ports (cmos): 45 (42 ports also serve as peripherals and 8 ports are also an n-ch open-drain type.) 8-bit pwm timer 8-bit interval timer operation (square output capable, operating clock cycle: 0.4 m s to 3.3 ms) 1 channel 7/8-bit resolution pwm operation (conversion cycle: 51.2 m s to 839 ms) 1 channel timers 8-bit timer operation (operating clock cycle) 2 channels 16-bit timer operation (operating clock cycle) 1 channel 8-bit serial i/o 8 bits lsb first/msb first selectable one clock selectable from four operation clocks (one external shift clock, three internal shift clocks: 0.8 m s, 3.2 m s, 12.8 m s) lcd controller 24 segments 4 commons 10-bit a/d converter 10-bit resolution 8 channels a/d conversion mode (conversion time: 13.2 m s) sense mode (conversion time: 7.2 m s) op amps 4 channels the output can be used for a/d converter input. mb89875 part number parameter
3 mb89870 series (continued) * : varies with conditions such as the operating frequency. (see section n electrical characteristics.) n package and corresponding products : available : not available note: for more information about each package, see section n package dimensions. MB89P875 mb89pv870 external interrupt 8 independent channels (edge selection, interrupt vector, and source flag) rising edge/falling edge selectable (4 channels) rising edge/falling edge/both edges selectable (4 channels) used also for wake-up from stop/sleep mode (edge detection is also permitted in stop mode.) low-power consumption (standby mode) subclock mode, sleep mode, watch mode, and stop mode process cmos operating voltage* 2.2 v to 6.0 v 2.7 v to 6.0 v eprom for use package mb89875 MB89P875 mb89pv870 fpt-80p-m05 fpt-80p-m06 mqp-80c-p01 mb89875 mbm27c256a-20tv part number parameter
4 mb89870 series n differences among products 1. memory size before evaluating using the piggyback product, verify its differences from the product that will actually be used. take particular care on the following points: ? on the mb89pv870, the program area starts from address 8006 h but on the MB89P875 and mb89875 starts from 8000 h . (on the MB89P875, addresses bff0 h to bff6 h comprise the option setting area, option settings can be read by reading these addresses. on the mb89pv870 and mb89875, addresses 8000 h to 8006 h could also be used as a program rom. however, do not use these addresses in order to maintain compatibility of the MB89P875.) 2. current consumption ? in the case of the mb89pv870, add the current consumed by the eprom which is connected to the top socket. ? when operated at low speed, the product with an otprom (one-time prom) or an eprom will consume more current than the product with a mask rom. however, the current consumption in sleep/stop modes is the same. (for more information, see sections n electrical characteristics and n example characteristics.) 3. mask options functions that can be selected as options and how to designate these options vary by the product. before using options check section n mask options. take particular care on the following points: ? a pull-up resistor cannot be selectable for p30 to p37 if they are used as the analog input pin for an a/d converter. ? a pull-up resistor cannot be selectable for p10 to p17, and p34 to p37 if an op amp is used. ? a pull-up resistor is not selectable for p40 to p47 and p23, p24 if they are used as lcd pins. ? options are fixed on the mb89pv870.
5 mb89870 series n pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 seg1 seg0 com0 com1 com2/p24 com3/p23 v3 v cc v2 v1 v0 v ss p22 p21 p20 x1a x0a p57/sck p56/so p55/si 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p45/seg21 p44/seg20 p43/seg19 p42/seg18 p41/seg17 p40/seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 (top view) (fpt-80p-m05) p46/seg22 p47/seg23 av ss avr av cc p30/an0 p31/an1 p32/an2 p33/an3 p34/an4/out0 p35/an5/out1 p36/an6/out2 v ss p37/an7/out3 x1 x0 mod1 mod0 rst p00/int0 p01/int1 p02/int2 p03/int3 p04/int4 p05/int5 p06/int6 p07/int7 p11/in0+ p13/in1+ p15/in2+ p17/in3+ p50/pwm p51/to2 p52/to1 p53/ec p54/buz p10/in0 p14/in2 p12/in1 p16/in3
6 mb89870 series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p44/seg20 p45/seg21 p46/seg22 p47/seg23 av ss avr av cc p30/an0 p31/an1 p32/an2 p33/an3 p34/an4/out0 p35/an5/out1 p36/an6/out2 v ss p37/an7/out3 x1 x0 mod1 mod0 rst p00/int0 p01/int1 p02/int2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 seg3 seg2 seg1 seg0 com0 com1 com2/p24 com3/p23 v3 v cc v2 v1 v0 v ss p22 p21 p20 x1a x0a p57/sck p56/so p55/si p54/buz p53/ec 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p43/seg19 p42/seg18 p41/seg17 p40/seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p03/int3 p04/int4 p05/int5 p06/int6 p07/int7 p11/in0+ p13/in1+ p15/in2+ p17/in3+ p50/pwm p51/to2 p52/to1 (top view) (fpt-80p-m06) p10/in0 p12/in1 p14/in2 p16/in3
7 mb89870 series pin assignment on package top (mb89pv870 only) n.c.: internally connected. do not use. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 81 n.c. 89 a2 97 n.c. 105 oe 82 v pp 90 a1 98 o4 106 n.c. 83 a12 91 a0 99 o5 107 a11 84 a7 92 n.c. 100 o6 108 a9 85 a6 93 o1 101 o7 109 a8 86 a5 94 o2 102 o8 110 a13 87 a4 95 o3 103 ce 111 a14 88 a3 96 v ss 104 a10 112 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p44/seg20 p45/seg21 p46/seg22 p47/seg23 av ss avr av cc p30/an0 p31/an1 p32/an2 p33/an3 p34/an4/out0 p35/an5/out1 p36/an6/out2 v ss p37/an7/out3 x1 x0 mod1 mod0 rst p00/int0 p01/int1 p02/int2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 seg3 seg2 seg1 seg0 com0 com1 com2/p24 com3/p23 v3 v cc v2 v1 v0 v ss p22 p21 p20 x1a x0a p57/sck p56/so p55/si p54/buz p53/ec 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p43/seg19 p42/seg18 p41/seg17 p40/seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p03/int3 p04/int4 p05/int5 p06/int6 p07/int7 p11/in0+ p13/in1+ p15/in2+ p17/in3+ p50/pwm p51/to2 p52/to1 (top view) 101 102 103 104 105 106 107 108 109 93 92 91 90 89 88 87 86 85 100 99 98 97 96 95 94 110 111 112 81 82 83 84 (mqp-80c-p01) p10/in0 p12/in1 p14/in2 p16/in3 each pin inside the dashed line is for the mb89pv870 only.
8 mb89870 series n pin description (continued) *1: fpt-80p-m05 *2: fpt-80p-m06 *3: mqp-80c-p01 pin no. pin name circuit type function lqfp *1 qfp *2 mqfp *3 15 17 x1 a main clock crystal oscillator pins (max. 10 mhz) 16 18 x0 44 46 x0a b subclock crystal oscillator pins (32.768 khz) 45 47 x1a 17 19 mod1 c operating mode selection pins connect to v ss (gnd) when using. 18 20 mod0 19 21 rst j reset i/o pin l is output from this pin by an internal source. the internal circuit is initialized by the input of l. 20 to 27 22 to 29 p00/int0 to p07/int7 d general-purpose i/o ports also serve as an external interrupt input (wake-up function). external interrupt input is hysteresis input. 28, 29, 30, 31, 32, 33, 34, 35 30, 31, 32, 33, 34, 35, 36, 37 p10/in0C, p11/in0+, p12/in1C, p13/in1+, p14/in2C, p15/in2+, p16/in3C, p17/in3+ e general-purpose i/o ports also serve as the input for the op amp 46 to 48 48 to 50 p20 to p22 f general-purpose i/o ports 6 to 9 8 to 11 p30/an0 to p33/an3 e general-purpose i/o ports also serve as the input for the a/d converter. 10 to 14 12 to 16 p34/an4/out0 to p37/an7/out3 g general-purpose i/o ports also serve as the a/d converter input and the output for the op amp. 75 to 80, 1,2 77 to 80, 1 to 4 p40/seg16 to p47/seg23 h general-purpose i/o ports also serve as an lcd controller/driver segment output. 36 38 p50/pwm f general-purpose i/o port the output type can be switched between n-ch open-drain and cmos. also serves as an 8-bit pwm timer. 37, 38, 39 39, 40, 41 p51/to2, p52/to1, p53/ec f general-purpose i/o ports the output type can be switched between n-ch open-drain and cmos. also serves as an 8/16-bit timer/counter.
9 mb89870 series (continued) *1: fpt-80p-m05 *2: fpt-80p-m06 *3: mqp-80c-p01 pin no. pin name circuit type function lqfp *1 qfp *2 mqfp *3 40 42 p54/buz f general-purpose i/o port the output type can be switched between n-ch open-drain and cmos. also serves as a buzzer output. 41, 42, 43 43, 44, 45 p55/si, p56/so, p57/sck f general-purpose i/o ports the output type can be switched between n-ch open-drain and cmos. also serve as an 8-bit serial i/o. 59 to 74 61 to 76 seg15 to seg0 i lcd controller/driver segment output pins 58, 57 60, 59 com0, com1 i lcd controller/driver common output pins 56, 55 58, 57 com2/p24, com3/p23 h lcd controller/driver common output pins these pins can be used as general-purpose i/o ports when they are not used as common output pins. 50 to 54 52 to 56 v3 to v0 lcd driving power supply pins 57av cc a/d converter and op amp power supply pin 4 6 avr a/d converter reference voltage input pin 35av ss a/d converter and op amp power supply (gnd) pin 53 55 v cc power supply pin 13, 49 15, 51 v ss power supply (gnd) pins
10 mb89870 series ? external eprom pins (mb89pv870 only) pin no. pin name i/o function 82 v pp o h level output pin 83 84 85 86 87 88 89 90 91 a12 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins 93 94 95 o1 o2 o3 i data input pins 96 v ss o power supply (gnd) pin 98 99 100 101 102 o4 o5 o6 o7 o8 i data input pins 103 ce o rom chip enable pin outputs h during standby. 104 a10 o address output pin 105 oe o rom output enable pin outputs l at all times. 107 108 109 a11 a9 a8 o address output pins 110 a13 o 111 a14 o 112 v cc o eprom power supply pin 81 92 97 106 n.c. internally connected pins be sure to leave them open.
11 mb89870 series n i/o circuit type (continued) type circuit remarks a main clock ? at an oscillation feedback resistor of approximately 1 m w /5.0 v b subclock ? at an oscillation feedback resistor of approximately 4.5 m w /5.0 v c ? cmos hysteresis input d ? cmos i/o (when selected as general-purpose ports) ? hysteresis input (when selected as an external interrupt input) ? pull-up resistor optional at approximately 50 k w /5.0 v e ? analog input ? cmos i/o (when selected as general-purpose ports) ? pull-up resistor optional at approximately 50 k w /5.0 v x1 x0 main clock control signal n-ch p-ch p-ch n-ch x1a x0a subclock control signal n-ch n-ch p-ch p-ch p-ch n-ch r p-ch p-ch r analog input p-ch n-ch p-ch n-ch
12 mb89870 series (continued) type circuit remarks f ? cmos i/o (when selected as general-purpose ports) ? p50 to p57 are output only and can be switched between cmos output and n-ch open-drain output. ? pull-up resistor optional at approximately 50 k w /5.0 v g ? analog input ? analog output ? cmos i/o (when selected as general-purpose ports) ? pull-up resistor optional at approximately 50 k w /5.0 v h ? lcd controller/driver output ? cmos i/o (when selected as general-purpose ports) ? pull-up resistor optional at approximately 50 k w /5.0 v i ? lcd controller/driver output j ? at an output pull-up resistor (p-ch) of approximately 50 k w /5.0 v ? cmos hysteresis input p-ch n-ch r p-ch p-ch r analog output analog output p-ch n-ch p-ch n-ch p-ch r p-ch n-ch p-ch p-ch n-ch n-ch n-ch n-ch p-ch p-ch p-ch n-ch r
13 mb89870 series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d and d/a converters connect to be av cc = davc = v cc and av ss = avr = v ss even if the a/d and d/a converters are not in use. 4. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 6. precautions when using an external clock when an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode.
14 mb89870 series n programming to the eprom on the MB89P875 the MB89P875 is an otprom version of the mb89870 series. 1. features ? 16-kbyte prom on chip ? options can be set using the eprom programmer. ? equivalency to the mbm27c256a in eprom mode (when programmed with the eprom programmer) 2. memory space memory space in each mode such as 16-kbyte prom, option area is diagrammed below. 3. programming to the eprom in eprom mode, the MB89P875 functions equivalent to the mbm27c256a. this allows the prom to be programmed with a general-purpose eprom programmer (the electronic signature mode cannot be used) by using the dedicated socket adapter. when the operating rom area for a single chip is 16 kbytes (c000 h to ffff h ) the prom can be programmed as follows: programming procedure (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 4000 h to 7fff h (note that addresses c000 h to ffff h while operating as a single chip assign to 4000 h to 7fff h in eprom mode). load option data into addresses 3ff0 h to 3ff6 h of the eprom programmer. (for information about each corresponding option, see 7. setting otprom options.) (3) program to 3ff0 h to 7fff h with the eprom programmer. 0000 h 0080 h 0280 h c000 h i/o not available prom 16 kb ffff h single chip bff6 h 4000 h 7fff h 3ff0 h not available ram eprom mode (corresponding address on the eprom programmer) address eprom 16 kb vacancy option area 3ff6 h not available bff0 h
15 mb89870 series 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. 5. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 6. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel (81)-3-3986-0403 fax (81)-3-5396-9106 minato electronics inc.: tel: usa (1)-916-348-6066 japan (81)-45-591-5611 advantest corp.: tel: except japan (81)-3-3930-4111 part no. package compatible socket adapter sun hayato co., ltd. recommended programmer manufacturer and programmer name minato electronics inc. advantest corp. 1890a r4945a MB89P875pfv lqfp-80 rom-80sqf-28dp-8l recommended recommended MB89P875pf qfp-80 rom-80qf-28dp-8l3 recommended recommended program, verify aging +150?, 48 hrs. data verification assembly
16 mb89870 series 7. setting otprom options the programming procedure is the same as that for the prom. options can be set by programming values at the addresses shown on the memory map. the relationship between bits and options is shown on the following bit map: ? otprom option bit map note: each bit is set to 1 as the initialized value. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 3ff0 h vacancy readable and writable vacancy readable and writable vacancy readable and writable single/dual- clock system 1: dual clock 0: single clock reset pin output 1: yes 0: no power-on reset 1: yes 0: no oscillation stabilization time 00: 2 18 /f ch 10: 2 13 /f ch 01: 2 17 /f ch 11: 0 3ff1 h p07 pull-up 1: no 0: yes p06 pull-up 1: no 0: yes p05 pull-up 1: no 0: yes p04 pull-up 1: no 0: yes p03 pull-up 1: no 0: yes p02 pull-up 1: no 0: yes p01 pull-up 1: no 0: yes p00 pull-up 1: no 0: yes 3ff2 h vacancy readable and writable vacancy readable and writable p44 to p47 pull-up 1: no 0: yes p40 to p43 pull-up 1: no 0: yes p16, p17 pull-up 1: no 0: yes p14, p15 pull-up 1: no 0: yes p12, p13 pull-up 1: no 0: yes p10, p11 pull-up 1: no 0: yes 3ff3 h p37 pull-up 1: no 0: yes p36 pull-up 1: no 0: yes p35 pull-up 1: no 0: yes p34 pull-up 1: no 0: yes p33 pull-up 1: no 0: yes p32 pull-up 1: no 0: yes p31 pull-up 1: no 0: yes p30 pull-up 1: no 0: yes 3ff4 h p57 pull-up 1: no 0: yes p56 pull-up 1: no 0: yes p55 pull-up 1: no 0: yes p54 pull-up 1: no 0: yes p53 pull-up 1: no 0: yes p52 pull-up 1: no 0: yes p51 pull-up 1: no 0: yes p50 pull-up 1: no 0: yes 3ff5 h vacancy readable and writable vacancy readable and writable vacancy readable and writable p24 pull-up 1: no 0: yes p23 pull-up 1: no 0: yes p22 pull-up 1: no 0: yes p21 pull-up 1: no 0: yes p20 pull-up 1: no 0: yes 3ff6 h vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable reserved bit readable and writable
17 mb89870 series n programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c256a-20tv 2. programming socket adapter to program to the prom using an eprom programmer, use the socket adapter (manufacturer: sun hayato co., ltd.) listed below. inquiry: sun hayato co., ltd.: tel (81)-3-3986-0403 fax (81)-3-5396-9106 3. memory space memory space in 32-kbyte prom is diagrammed below. 4. programming to the eprom (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0006 h to 7fff h . (3) program to 0000 h to 7fff h with the eprom programmer. package compatible socket part number lcc-32 (rectangle) rom-32lc-28dp-yg lcc-32 (square) rom-32lc-28dp-s 0000 h 0080 h 0480 h i/o not available prom 32 kb ffff h 8006 h 7fff h 0000 h ram corresponding addresses on the eprom programmer single chip prom 32 kb not available 0006 h not available 8000 h address
18 mb89870 series n block diagram x0 x1 timebase timer clock controller seg0 to seg15 i/o port lcd controller/driver v0 to v3 ram rom mod 2, v cc 1 v ss 2 av cc , av ss , avr other pins internal bus 8-bit serial i/o buzzer output 8-bit timer/counter 1 8-bit timer/counter 2 8-bit pwm timer p50/pwm i/o port lcd display ram (12 8 bits) 4 16 com0, com1 2 2 com2/p24, com3/p23 8 p40/seg16 to p47/seg23 8 reset circuit (watchdog) x0a x1a subclock oscillator (32.768 khz) main clock oscillator rst p51/to2 p52/to1 p53/ec p54/buz p55/si p56/so p57/sck p20 to p22 p00/int0 to p07/int7 p30/an0 to p33/an3 com: 2 to 4 seg: 16 to 24 p10/in0 p11/in0+ p12/in1 p13/in1+ p14/in2 p15/in2+ p16/in3 p17/in3+ p37/an7/out3 p36/an6/out2 p35/an5/out1 i/o port i/o port external interrupt 10-bit a/d converter + + + + 4 4 8 8 3 p34/an4/out0 f 2 mc-8l cpu
19 mb89870 series n cpu core 1. memory space the microcontrollers of the mb89870 series offer a memory space of 64 kbytes for storing all of i/o, data, and program areas. the i/o area is located at the lowest address. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89870 series is structured as illustrated below. memory space 0000 h 0080 h 0100 h 0480 h i/o ram 1 kb register 0000 h 0080 h 0100 h 0200 h c000 h mb89875 i/o ram 512 b register rom 16 kb external rom 32 kb 0000 h 0080 h 0100 h 0200 h MB89P875 i/o ram 512 b register prom 16 kb ffff h not available 0280 h 0200 h bff0 h c000 h not available not available mb89pv870 ffff h ffff h 0280 h not available 8000 h
20 mb89870 series 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a 16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a 16-bit register for index modification extra pointer (ep): a 16-bit pointer for indicating a memory address stack pointer (sp): a 16-bit register for indicating a stack area program status (ps): a 16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status pc a t ix ep sp ps 16 bits initial value fffd h indeterminate indeterminate indeterminate indeterminate indeterminate i-flag = 0, il1,0 = 11 the other bit values are indeterminate. structure of the program status register vacancy h i il1, 0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr vacancy vacancy
21 mb89870 series the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set to 1 when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared to 0 otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is enabled when this flag is set to 1. interrupt is disabled when the flag is cleared to 0. cleared to 0 at the reset. il1, 0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set to 1 if the msb becomes to 1 as the result of an arithmetic operation. cleared to 0 when the bit is cleared to 0. z-flag: set to 1 when an arithmetic operation results in 0. cleared otherwise. v-flag: set to 1 if the complement on 2 overflows as a result of an arithmetic operation. cleared to 0 if the overflow does not occur. c-flag: set to 1 when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to 0 otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low 01 10 2 11 3 rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 lower op codes rp generated addresses
22 mb89870 series the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers and up to a total of 32 banks can be used on the mb89875 (ram 512 8 bits). the bank currently in use is indicated by the register bank pointer (rp). note: the number of register banks that can be used varies with the ram size. r 1 r 2 r 3 r 4 r 5 r 6 r 7 this address = 0100 h + 8 (rp) memory area 32 banks r 0 register bank configuraiton
23 mb89870 series n i/o map (continued) address read/write register name register description 00 h r/w pdr0 port 0 data register 01 h w ddr0 port 0 data direction register 02 h r/w pdr1 port 1 data register 03 h w ddr1 port 1 data direction register 04 h r/w pdr2 port 2 data register 05 h r/w ddr2 port 2 data direction register 06 h vacancy 07 h r/w scc system clock control register 08 h r/w smc standby control register 09 h r/w wdte watchdog timer control register 0a h r/w tbcr timebase timer control register 0b h r/w wcr watch prescaler control register 0c h r/w pdr3 port 3 data register 0d h r/w ddr3 port 3 data direction register 0e h r/w pdr4 port 4 data register 0f h r/w ddr4 port 4 data direction register 10 h vacancy 11 h vacancy 12 h vacancy 13 h vacancy 14 h vacancy 15 h vacancy 16 h r/w pdr5 port 5 data register 17 h r/w ddr5 port 5 data direction register 18 h vacancy 19 h vacancy 1a h r/w chg5 port 5 switching register 1b h vacancy 1c h vacancy 1d h w icr3 port 3 input control register 1e h r/w cntr pwm control register 1f h w comp pwm compare register
24 mb89870 series (continued) note: do not use vacancies. address read/write register name register description 20 h vacancy 21 h vacancy 22 h vacancy 23 h vacancy 24 h r/w t2cr timer 2 control register 25 h r/w t1cr timer 1 control register 26 h r/w t2dr timer 2 data register 27 h r/w t1dr timer 1 data register 28 h r/w smr serial mode register 29 h r/w sdr serial data register 2a h vacancy 2b h vacancy 2c h r/w opc op amp control register 2d h r/w adc1 a/d converter control register 1 2e h r/w adc2 a/d converter control register 2 2f h r/w adch a/d converter data register h 30 h r/w adcl a/d converter data register l 31 h r/w eie1 external interrupt 1 enable register 32 h r/w eif1 external interrupt 1 flag register 33 h r/w eie2 external interrupt 2 enable register 34 h to 5f h vacancy 60 h to 6b h r/w vram display data ram 6c h to 6f h vacancy 70 h r/w lcr1 lcd controller/driver control register 1 71 h r/w lcr2 lcd controller/driver control register 2 72 h to 7b h vacancy 7c h w ilr1 interrupt level setting register 1 7d h w ilr2 interrupt level setting register 2 7e h w ilr3 interrupt level setting register 3 7f h vacancy
25 mb89870 series n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) * : use av cc and v cc set at the same voltage. take care so that avr does not exceed av cc + 0.3 v and av cc does not exceed v cc , such as when power is turned on. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage v cc av cc v ss C 0.3 v ss + 7.0 v * a/d converter reference input voltage avr v ss C 0.3 v ss + 7.0 v lcd power supply voltage v0 to v3 v ss C 0.3 v ss + 7.0 v v0 to v3 must not exceed v cc . input voltage v i v ss C 0.3 v cc + 0.3 v output voltage v o v ss C 0.3 v cc + 0.3 v l level maximum output current i ol ? 20 ma l level average output current i olav ? 4ma average value (operating current operating rate) l level total maximum output current ? i ol ? 100 ma l level total average output current ? i olav ? 40 ma average value (operating current operating rate) h level maximum output current i oh ? C20 ma h level average output current i ohav ? C4 ma average value (operating current operating rate) h level total maximum output current ? i oh ? C50 ma h level total average output current ? i ohav ? C20 ma average value (operating current operating rate) power consumption p d ? 300 mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
26 mb89870 series 2. recommended operating conditions (av ss = v ss = 0.0 v) * : these values vary with the operating frequency, instruction cycle, and analog assurance range. see figure 1 and 5. a/d converter electrical characteristics. parameter symbol value unit remarks min. max. power supply voltage v cc av cc 2.2* 6.0* v normal operation assurance range* mb89875 2.7 6.0 v normal operation assurance range mb89pv870/p875 1.5 6.0 v retains the ram state in stop mode a/d converter reference input voltage avr 0.0 av cc v lcd power supply voltage v0 to v3 v ss v cc v lcd power supply range (the optimum value is dependent on the lcd element in use.) operating temperature t a C40 +85 c
27 mb89870 series figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/f ch . since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. 1 2 3 4 5 6 1.0 10.0 operation assurance range operating voltage (v) 5.0 main clock operating frequency (at an instruction cycle of 4/f ch ) (mhz) note: the shaded area is assured only for the mb89875. 2.0 3.0 4.0 6.0 7.0 8.0 9.0 analog accuracy assured in the av cc = 3.5 v to 6.0 v range 4.0 0.8 2.0 0.4 minimum execution time (instruction cycle) (ms) figure 1 operating voltage vs. main clock operating frequency
28 mb89870 series 3. dc characteristics (av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin name condition value unit remarks min. typ. max. h level input voltage v ih p20 to p24, p30 to p37, p40 to p47, p50 to p52, p54, p56 ? 0.7 v cc ? v cc + 0.3 v v ihs p00 to p07, p10 to p17, mod0, mod1, rst , p53, p55, p57 ? 0.8 v cc ? v cc + 0.3 v l level input voltage v il p20 to p24, p30 to p37, p40 to p47, p50 to p52, p54, p56 ? v ss - 0.3 ? 0.3 v cc v v ils p00 to p07, p10 to p17, mod0, mod1, rst , p53, p55, p57 v ss - 0.3 ? 0.2 v cc v open-drain output pin application voltage v d p50 to p57 v ss - 0.3 ? v cc C 0.3 v n-ch open- drain h level output voltage v oh p00 to p07, p10 to p17, p20 to p24, p30 to p37, p40 to p47, p50 to p57 i oh = C2.0 ma 4.0 ?? v l level output voltage v ol p00 to p07, p10 to p17, p20 to p24, p30 to p37, p40 to p47, p50 to p57 i ol = 4.0 ma ?? 0.4 v input leakage current (hi-z output leakage current) i li p00 to p07, p10 to p17, p20 to p24, p30 to p37, p40 to p47, p50 to p57 mod0, mod1, rst 0.0 v < v i < v cc ?? 5 m a with pull-up resistor pull-up resistance r pull p00 to p07, p10 to p17, p20 to p24, p30 to p37, p40 to p47, p50 to p57 v i = 0.0 v 25 50 100 k w with pull-up resistor
29 mb89870 series (av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin name condition value unit remarks min. typ. max. power supply current *1 i cc1 v cc f ch = 10 mhz v cc = 5.0 v t inst *2 = 0.4 m s 1220ma i cc2 f ch = 10 mhz v cc = 3.0 v t inst *2 = 6.4 m s 1.0 2ma mb89875/ pv870 1.5 2.5 ma MB89P875 i ccs1 f ch = 10 mhz v cc = 5.0 v t inst *2 = 0.4 m s 3 7ma i ccs2 f ch = 10 mhz v cc = 3.0 v t inst *2 = 6.4 m s 0.51.5ma i ccl f cl = 32.768 khz, v cc = 3.0 v subclock mode 50100 m a mb89875/ pv870 500700 m a MB89P875 i ccls f cl = 32.768 khz, v cc = 3.0 v subclock sleep mode 1550 m a i cct f cl = 32.768 khz, v cc = 3.0 v ? watch mode ? main clock stop mode at dual- clock system 315 m a i cch t a = +25 c ? subclock stop mode ? main clock stop mode at single- clock system 1 m a i a av cc f ch = 10 mhz, when a/d conversion is activated 1.5 3ma i ah f ch = 10 mhz, t a = +25 c, when a/d conversion is stopped 1 m a sleep mode
30 mb89870 series (continued) (av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) *1: the power supply current is measured at the external clock. *2: for information on t inst , see (4) instruction cycle in 4. ac characteristics. note: for pins which serve as the lcd and ports (p23, p24 and p40 to p47), see the port parameter when these pins are used as ports and the lcd parameter when they are used as lcd pins. parameter symbol pin name condition value unit remarks min. typ. max. lcd divided resistance r lcd ? between v cc and v0 at v cc = 5.0 v 300 500 750 k w com0 to 3 output impedance r vcom com0 to 3 v1 to v3 = 5.0 v ? 2.5 k w seg0 to 24 output impedance r vseg seg0 to 24 ? 15 k w lcd controller/ driver leakage current i lcdl v0 to v3, com0 to 3 seg0 to seg24 ? ? 1 m a input capacitance c in other than av cc , av ss , v cc , and v ss f = 1 mhz 10 ? pf
31 mb89870 series 4. ac characteristics (1) reset timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (2) power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol condition value unit remarks min. max. rst l pulse width t zlzh 48 t hcyl ns parameter symbol condition value unit remarks min. max. power supply rising time t r 50 ms power-on reset function only power supply cutoff time t off 1 ms due to repeated operations 0.2 v cc 0.2 v cc rst t zlzh 0.2 v 0.2 v 2.0 v 0.2 v t r v cc t off
32 mb89870 series (3) clock timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. typ. max. clock frequency f ch x0, x1 110mhz f cl x0a, x1a 32.768 khz clock cycle time t hcyl x0, x1 100 1000 ns t lcyl x0a, x1a 30.5 m s input clock pulse width p wh p wl x0 20 ns external clock input clock rising/ falling time t cr t cf x0 10 ns external clock
33 mb89870 series 0.2 v cc x0 0.2 v cc x0 x1 t hcyl when a crystal or ceramic resonator is used x0 x1 when an external clock is used open 0.2 v cc 0.8 v cc 0.8 v cc t cr t cf p wl p wh x0 and x1 timing and conditions main clock conditions 0.2 v cc x0a 0.2 v cc x0a x1a when a crystal or ceramic resonator is used t lcyl x0a and x1a timing and conditions subclock conditions
34 mb89870 series (4) instruction cycle note: when operating at 10 mhz, the cycle varies with the set execution time. (5) serial i/o timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f ch , 8/f ch , 16/f ch , 64/f ch m s (4/f ch ) t inst = 0.4 m s when operating at f ch = 10 mhz 2/f cl m s t inst = 61.036 m s when operating at f cl = 32.768 khz parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc sck internal shift clock mode 2 t inst * m s sck ? so time t slov sck, so C200 200 ns valid si ? sck - t ivsh si, sck 1/2 t inst * m s sck - ? valid si hold time t shix sck, si 1/2 t inst * m s serial clock h pulse width t shsl sck external shift clock mode 1 t inst * m s serial clock l pulse width t slsh 1 t inst * m s sck ? so time t slov sck, so 0 200 ns valid si ? sck - t ivsh si, sck 1/2 t inst * m s sck - ? valid si hold time t shix sck, si 1/2 t inst * m s t scyc t slov t shix t ivsh sck 2.4 v 0.8 v 0.8 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc so si t slsh t slov t shix t ivsh sck 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc so si 0.2 v cc t shsl 0.8 v cc internal shift clock mode external shift clock mode
35 mb89870 series (6) peripheral input timing (v cc = +5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst, see (4) instruction cycle. parameter symbol pin name value unit remarks min. max. peripheral input h pulse width 1 t ilih1 ec 1 t inst * m s peripheral input l pulse width 1 t ihil1 1 t inst * m s peripheral input h pulse width 2 t ilih2 int7 to int0 2 t inst * m s peripheral input l pulse width 2 t ihil2 2 t inst * m s 0.2 v cc 0.8 v cc t ihil1 ec 0.2 v cc t ilih1 int7 to int0 0.8 v cc 0.2 v cc 0.8 v cc t ihil2 0.2 v cc t ilih2 0.8 v cc
36 mb89870 series 5. a/d converter electrical characteristics (av cc = v cc = +3.5 v to +6.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle in 4. ac characteristics. 6. a/d converter glossary ? resolution analog changes that are identifiable with the a/d converter when the number of bits is 10, analog voltage can be divided into 2 10 = 1024. ? linearity error (unit: lsb) the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1111 ? 11 1111 1110) from actual conversion characteristics ? differential linearity error (unit: lsb) the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value ? total error (unit: lsb) the difference between theoretical and actual conversion values parameter symbol pin name condition value unit remarks min. typ. max. resolution 10bit total error avr = av cc 3.0 lsb linearity error 2.0 lsb differential linearity error 1.5 lsb zero transition voltage v ot av ss C 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv full-scale transition voltage v fst avr C 3.5 lsb avr C 1.5 lsb avr + 0.5 lsb mv interchannel disparity 4.0lsb a/d mode conversion time 33 t inst * m s sense mode conversion time 18 t inst * m s analog port input current i ain an0 to an7 10 m a analog input voltage 0.0 avr v reference voltage avr 0.0 av cc v reference voltage supply current i r avr = 5.0 v, when a/d conversion is activated 200 ?m a i rh avr = 5.0 v, when a/d conversion is stopped 1 m a
37 mb89870 series 7. notes on using a/d converter ? input impedance of the analog input pins the a/d converter used for the mb89870 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating a/d conversion. for this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. therefore, it is recommended to keep the output impedance of the external circuit low (below 10 k w ). note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about 0.1 m f for the analog input pin. ?error the smaller the | avr C av ss |, the greater the error would become relatively. v ot v nt v (n + 1)t v fst digital output (1 lsb n + v ot ) 00 0000 00 0000 00 0000 0000 0001 0010 11 1111 11 1111 1110 1111 1 lsb = avr 1024 linearity error = differential linearity error = analog input actual conversion value theoretical conversion value total error = v nt ?(1 lsb n + v ot ) 1 lsb v ( n + 1 ) t ?v nt 1 lsb ?1 1 lsb v nt ?(1 lsb n + 1 lsb) linearity error sample hold circuit analog channel selector close for 8 instruction cycles after activating a/d conversion. if the analog input impedance is higher than 10 k w , it is recommended to connect an external capacitor of approx. 0.1 m f. analog input pin comparator r = 6 k w . . c = 33 pf . . analog input equivalent circuit
38 mb89870 series 8. op amp electrical characteristics (1) av cc = 5.0 v (av cc = v cc = 4.5 v to 5.5 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (2) av cc = 3.0 v (av cc = v cc = 2.7 v to 3.3 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. typ. max. i/o voltage range in0 to in3 0.5 v cc C 1.25 0.5 v cc 0.5 v cc + 1.25 v minimum load resistance 100 k w maximum load resistance 100 pf offset voltage C10 0 +10 mv gain-bandwidth production 1.8 mhz dc gain 75 db slew rate 0.9 v/ m s parameter symbol pin name condition value unit remarks min. typ. max. i/o voltage range in0 to in3 0.5 0.5 v cc C 0.35 v cc C 1.20 v minimum load resistance 250 k w maximum load resistance 100 m a offset voltage C10 0 +10 mv gain-bandwidth production 0.5 mhz dc gain 75 db slew rate 0.1 v/ m s
39 mb89870 series n example characteristics (1) l level output voltage (2) h level output voltage 0 0.0 0.5 1.0 1.5 2.5 2.0 3.5 3.0 4.0 5.0 4.5 v in (v) v in vs. v cc v ils v ihs 1234567 v cc (v) t a = +25? v ihs : v ils : threshold when input voltage in hysteresis characteristics is set to ??level threshold when input voltage in hysteresis characteristics is set to ??level 0 0.0 0.1 0.2 0.3 0.4 0.5 v ol (v) v ol vs. i ol v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v 123456789 10 i ol (ma) t a = +25 ? 0.0 0.0 0.1 0.2 0.3 0.5 0.4 0.7 0.6 0.8 1.0 0.9 v cc ?v oh (v) v cc ?v oh vs. i oh v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v ?.5 ?.0 ?.5 ?.0 ?.5 ?.0 i oh (ma) t a = +25 ? 012 3 456 7 v cc (v) 5.0 v in (v) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v in vs. v cc t a = +25 ? (3) h level input voltage/l level input voltage (cmos input) (4) h level input voltage/l level input voltage (hysteresis input)
40 mb89870 series (5) power supply current (external clock) (continued) 2.0 0 20 40 60 80 120 100 180 200 140 160 i ccl ( m a) i ccl vs. v cc 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v cc (v) t a = +25 ? 2.0 0 2 4 6 10 8 14 16 12 i cc (ma) i cc1 vs. v cc , i cc2 vs. v cc 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v cc (v) f ch = 10 mhz t a = +25? divide by 64 (i cc2 ) divide by 16 divide by 4 (i cc1 ) divide by 8 2.0 0 0.5 1.0 1.5 2.0 3.0 2.5 4.5 5.0 3.5 4.0 i ccs (ma) i ccs1 vs. v cc , i ccs2 vs. v cc 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v cc (v) f ch = 10 mhz t a = +25? divide by 64 (i cc2 ) divide by 16 divide by 8 divide by 4 (i cc1 ) 2.0 0 5 10 15 20 30 25 45 50 35 40 i ccls ( m a) i ccls vs. v cc 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v cc (v) t a = +25 ?
41 mb89870 series (continued) (6) pull-up resistance 2.0 0 2 4 6 8 12 10 18 20 14 16 i cct ( m a) i cct vs. v cc 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 v cc (v) t a = +25 ?c i cch ( m a) v cc (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.4 0.8 1.2 1.6 2.0 t a = +25 ? i cch vs. v cc 6.0 6.5 0.2 0.6 1.0 1.4 1.8 i a (ma) av cc (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 t a = + 25 ? f ch = 10 mhz i a vs. av cc 2.0 0 20 40 60 80 120 100 180 200 140 160 i r ( m a) i r vs. avr 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 avr (v) t a = +25 ? 1 10 100 1000 r pull (k w ) r pull vs. v cc 23456 v cc (v) t a = +25 ?
42 mb89870 series n instructions (136 instructions) execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ?others table 1 lists symbols used for notation of instructions. table 1 instruction symbols symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits) ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
43 mb89870 series columns indicate the following: mnemonic: assembler notation of an instruction ~: the number of instructions #: the number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah prior to the instruction executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f.
44 mb89870 series table 2 transfer instructions (48 instructions) notes: during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
45 mb89870 series table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
46 mb89870 series (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
47 mb89870 series n instruction map 0123456789 abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep ,#d8 cmp @ep ,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel l h
48 mb89870 series n mask options notes: reset is input asynchronized with the internal clock whether with or without power-on reset. p30 to p37 should be set to without pull-up resistor when an a/d conveter is used. p10 to p17, p34 to p37 should be set to without pull-up resistor when an op amp is used. p40 to p47 and p23 and p24 should be set to without pull-up resistor when an lcd controller/driver is used. n ordering information no. part number mb89875 MB89P875 mb89pv870 specifying procedure specify when ordering masking set with eprom programmer setting not possible 1 pull-up resistors p00 to p07, p10 to p17, p20 to p24, p30 to p37, p40 to p47, p50 to p57 specify by pin (in 2-pin unit for p10 to p17, and in 4-pin unit for p40 to p47) specify by pin (in 2-pin unit for p10 to p17, and in 4-pin unit for p40 to p47) fixed to without pull- up resistor 2 power-on reset selection with power-on reset without power-on reset selectable selectable fixed to with power- on reset 3 selection of the oscillation stabilization time initial value 2 18 /f ch (approx. 26.2 ms) 2 17 /f ch (approx. 13.1 ms) 2 13 /f ch (approx. 0.8 ms) 2 4 /f ch (approx. 0 ms) selectable selectable fixed to 2 18 /f ch (approx. 26.2 ms) 4 selection either single- or dual-clock system single clock dual clock selectable selectable fixed to dual-clock system 5 reset pin output with reset output without reset output selectable selectable fixed to with reset output part number package remarks mb89875pfv MB89P875pfv 80-pin plastic lqfp (fpt-80p-m05) mb89875pf MB89P875pf 80-pin plastic qfp (fpt-80p-m06) mb89pv870cf 80-pin ceramic mqfp (mqp-80c-p01)
49 mb89870 series n package dimensions c 1994 fujitsu limited f80010s-3c-2 "b" 0.10(.004) 0.58(.023)max 0.18(.007)max details of "a" part 0 10 details of "b" part 12.00(.472) ref 16.30?.40 (.642?016) 0.05(.002)min (stand off) 0.15?.05(.006?002) index 23 . 90 0 . 40( . 941 ? 016) 20.00?.20(.787?008) 17.90?.40 14.00?.20 (.551?008) (.705?016) 0.80(.0315)typ 0.35?.10 (.014?004) 0.16(.006) m 18.40(.724)ref 22.30?.40(.878?016) 1 24 25 40 41 64 65 80 0.25(.010) 0.30(.012) 0.80?.20 (.031?008) lead no. "a" 3 . 35( . 132)max (mounting height) c 1995 fujitsu limited f80008s-2c-5 0.10(.004) 0.50?.20(.020?008) 0.10?.10 (.004?004) details of "a" part 0 10 14.00?.20(.551?008)sq 12.00?.10(.472?004)sq 9.50 13.00 (.374) ref (.512) nom 0.50?.08 (.0197?0031) .007 ?001 +.003 ?.03 +0.08 0.18 .005 ?001 +.002 ?.02 +0.05 0.127 .059 ?004 +.008 ?.10 +0.20 1.50 "a" 80 120 21 41 60 61 40 index (stand off) lead no. (mounting height) dimensions in mm (inches) 80-pin plastic lqfp (fpt-80p-m05) dimensions in mm (inches) 80-pin plastic qfp (fpt-80p-m06)
50 mb89870 series c 1994 fujitsu limited m80001sc-4-2 15.58?.20 (.613?008) 16.30?.33 (.642?013) 18.70(.736)typ index area 0.30(.012) typ 1.27?.13 (.050?005) 22.30?.33 (.878?013) 24.70(.972) typ 10.16(.400) typ 12.02(.473) typ 14.22(.560) typ 18.12?.20 (.713?008) 1.27?.13 (.050?005) 0.30(.012)typ 7.62(.300)typ 9.48(.373)typ 11.68(.460)typ 0.15?.05 (.006?002) 8.70(.343) max 0.40?.10 (.016?004) .047 ?008 +.016 ?.20 +0.40 1.20 0.40?.10 (.016?004) 18.40(.724) ref 0.80?.25 (.0315?010) 12.00(.472)typ .047 ?008 +.016 ?.20 +0.40 1.20 0.80?.25 (.0315?010) 1.50(.059) typ 1.00(.040) typ 1.00(.040)typ 1.50(.059)typ index area 6.00(.236) typ 4.50(.177) typ index dimensions in mm (inches) 80-pin ceramic mqfp (mqp-80c-p01)
51 mb89870 series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9812 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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